The transmission rates for local area networks (LANs) that use unshielded twisted pair (UTP) copper cabling have progressively increased from 10 Megabits-per-second (Mbps) to 1 Gigabit-per-second (Gbps). The Gigabit Ethernet 1000 Base-T standard, for example, operates at a clock rate of 125 MHz and uses UTP cabling of Category 5 with four pairs to transmit 1 Gbps. Trellis-coded modulation (TCM) is employed by the transmitter, in a known manner, to achieve coding gain The signals arriving at the receiver are typically corrupted by intersymbol interference (ISI), crosstalk, echo, and noise A major challenge for 1000 Base-T receivers is to jointly equalize the channel and decode the corrupted trellis-coded signals at the demanded clock rate of 125 MHz, as the algorithms for joint equalization and decoding incorporate non-linear feedback loops that cannot be pipelined.
Data detection is often performed using maximum likelihood sequence estimation, to produce the output symbols or bits. A maximum likelihood sequence estimator considers all possible sequences and determines which sequence was actually transmitted, in a known manner. The maximum likelihood sequence estimator is the optimum decoder and applies the well-known Viterbi algorithm to perform joint equalization and decoding. For a more detailed discussion of a Viterbi implementation of a maximum likelihood sequence estimator (MLSE), see Gerhard Fettweis and Heinrich Meyr, “High-Speed Parallel Viterbi Decoding Algorithm and VLSI-Architecture,” IEEE Communication Magazine (May 1991), incorporated by reference herein
In order to reduce the hardware complexity for the maximum likelihood sequence estimator that applies the Viterbi algorithm, a number of sub-optimal approaches which are referred to as reduced-state sequence estimation (RSSE) have been proposed. For a discussion of reduced state sequence estimation techniques, as well as the special cases of decision-feedback sequence estimation (DFSE) and parallel decision-feedback decoding (PDFD) techniques, see, for example, P. R Chevillat and E. Eleftheriou, “Decoding of Trellis-Encoded Signals in the Presence of Intersymbol Interference and Noise”, IEEE Trans Commun., vol. 37, 669-76, (July 1989), M. V. Eyuboglu and S U H. Qureshi, “Reduced-State Sequence Estimation For Coded Modulation On Intersymbol Interference Channels”, IEEE JSAC, vol. 7, 989-95 (August 1989), or A. Duel-Hallen and C. Heegard, “Delayed Decision-Feedback Sequence Estimation,” IEEE Trans Commun., vol. 37, pp. 428-436, May 1989, each incorporated by reference herein.
Generally, reduced state sequence estimation techniques reduce the complexity of the maximum likelihood sequence estimators by merging several states. The RSSE technique incorporates non-linear feedback loops that cannot be pipelined. The critical path associated with these feedback loops is the limiting factor for high-speed implementations.
U.S. patent application Ser. No. 09/326,785, filed Jun. 4, 1999 and entitled “Method and Apparatus for Reducing the Computational Complexity and Relaxing the Critical Path of Reduced State Sequence Estimation (RSSE) Techniques,” incorporated by reference herein, discloses a technique that reduces the hardware complexity of RSSE for a given number of states and also relaxes the critical path problem. U.S. patent application Ser. No. 09/471,920, filed Dec. 23, 1999, entitled “Method and Apparatus for Shortening the Critical Path of Reduced Complexity Sequence Estimation Techniques,” incorporated by reference herein, discloses a technique that improves the throughput of RSSE by pre-computing the possible values for the branch metrics in a look-ahead fashion to permit pipelining and the shortening of the critical path. The complexity of the pre-computation technique, however, increases exponentially with the length of the channel impulse response. In addition, the delay through the selection circuitry that selects the actual branch metrics among all precomputed ones increases with L, eventually neutralizing the speed gain achieved by the precomputation.
A need therefore exists for a technique that increases the throughput of RSSE algorithms using precomputations with only a linear increase in hardware complexity with respect to the look-ahead computation depth.